Method for manufacturing semiconductor integrated circuit device

ABSTRACT

The invention is provided to prevent breakage and separation of wiring of a semiconductor integrated circuit device such as a bit-line of a DRAM. An HDP silicone oxide film is deposited on a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell by means of high density plasma CVD technique, and subjected to RTA (heat treatment) at 750° C. The surface is polished, and then a capacitor to be connected to other source and drain region of the memory cell selection MISFET is formed. As the result, even when a tantalum oxide film that is an capacitance insulating film of the capacitor is subjected to heat treatment, the film stress exerted on the bit-line is reduced, and breakage and separation of the bit-line are prevented.

BACKGROUND OF THE INVENTION

[0001] This invention relates to a technique for manufacturing a semiconductor integrated circuit device, and more particularly relates to a technique that is effectively applied to form an insulating film on a metal wiring.

[0002] Recently the technique for making laminated structure of an element and wiring has been developed concomitantly with highly integration of LSI. Though elements are separated by an interlayer insulating film therebetween, but separation or breakage of wiring due to film stress of the conductive layer or interlayer insulating film, which is an element or wiring of a laminate, has been revealed as the lamination has been developed.

[0003] Particularly, in the case that the process involves high temperature heat treatment after the interlayer insulating film is formed on the top of wiring, such heat treatment causes increased film stress and results in problem of wiring separation or breakage.

[0004] For example, Japanese Published Unexamined Patent Application No. Hei 10(1998)-173049 discloses a technique in which BPSG (Boro-Phosphate-silicate glass) film 83 is coated on the surface of a bit-line wiring layer by means of CVD (Chemical Vapor Deposition) technique is described. Furthermore, in this patent application, the patent application discloses a technique that the use of a HDP-SiO (High Density Plasma Silicon Oxide) film used instead of a BPSG film allows high temperature treatment in the forming process to be eliminated and the thermal stress can be suppressed extremely.

[0005] Furthermore, Japanese Published Unexamined Patent Application No. Hei 11(1999)-243180 discloses a technique in which a third interlayer insulating film that is served to insulate between a bit-line 27 and a bottom electrode of a capacitor is formed of a silicone oxide film by means of plasma CVD technique wherein a special film forming condition is employed.

SUMMARY OF THE INVENTION

[0006] The inventors of the present invention have developed various techniques to improve the performance of the semiconductor integrated circuit device including techniques to dissolve the above-mentioned problem of wiring separation and breakage.

[0007] For example, a memory cell of a DRAM (Dynamic Random Access Memory) comprises a memory cell selection MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a capacitor (information storing capacitor element) that is connected in series to the memory cell selection MISFET, and a terminal that is not connected to the capacitor is connected to a bit-line.

[0008] In the case of so-called COB (capacitor over bit-line) structure among the DRAM structures, a capacitor is formed on the top of a bit-line and an interlayer insulating film is formed between the bit-line and capacitor as described hereinafter. As described hereinafter, the capacitor forming process includes high temperature heat treatment step, and breaking and separation of a bit-line is caused due to the difference in film stress between the bit-line and the interlayer insulating film.

[0009] It is an object of the present invention to relax the film stress of the wiring and an insulating film formed on the top thereof that are structural components of a semiconductor integrated circuit device and to prevent the breakage or separation of the wiring.

[0010] Furthermore, another object of the present invention is to improve the performance of a semiconductor integrated circuit device.

[0011] The above-mentioned objects, other objects, and novel features of the present invention will be apparent in the description of the present specification and attached drawings.

[0012] The outline of the representative inventions out of the inventions disclosed in the present patent application will be described briefly hereinafter.

[0013] (1) A method for manufacturing a semiconductor integrated circuit device of the present invention involves a successive process in which a second insulating film is formed at the first temperature so as to cover the wiring, the second insulating film is subjected to heat treatment at the second temperature that is higher than the first temperature, and then a first electrode, dielectric film, and second electrode are formed on the second insulating film.

[0014] (2) A method for manufacturing a semiconductor integrated circuit device of the present invention comprises the steps of forming a second insulating film so as to cover the wiring by means of chemical vapor deposition technique, forming a third insulating film, which is a coated film, on the second insulating film, and after heat-treating at the first temperature, forming a fourth insulating film on the third insulating film by means of chemical vapor deposition technique, and further forming a first electrode, dielectric film, and second electrode on the fourth insulating film, wherein the step for forming the dielectric film includes a step for heat-treating the dielectric film at the second temperature, wherein the first temperature is equal to or higher than the second temperature.

[0015] (3) A method for manufacturing a semiconductor integrated circuit device of the present invention comprises the steps of forming a second insulating film so as to cover the wiring, heat-treating the second insulating film at the first temperature, thereafter etching the second insulating film so that the surface of the wiring is exposed to form an aperture on the second insulating film, forming a first conductive layer inside the aperture at the second temperature by means of chemical vapor deposition technique, forming a second conductive layer on the first conductive layer, and polishing the first and second conductive layers so that the first and second conductive layers remain selectively inside the aperture, wherein the first temperature is equal to or higher than the second temperature.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016]FIG. 1 is a partial cross sectional view of a substrate showing the manufacturing method of a semiconductor integrated circuit device (DRAM) according to the embodiment 1 of the present invention;

[0017]FIG. 2 is a partial plan view of the substrate showing the manufacturing method of the semiconductor integrated circuit device (DRAM) according to the embodiment 1 of the present invention;

[0018]FIG. 3 is a partial cross sectional view of the substrate showing the manufacturing method of the semiconductor integrated circuit device (DRAM) according to the embodiment 1 of the present invention;

[0019]FIG. 4 is a partial plan view of the substrate showing the manufacturing method of the semiconductor integrated circuit device (DRAM) according to the embodiment 1 of the present invention;

[0020]FIG. 5 is a partial cross sectional view of the substrate showing the manufacturing method of the semiconductor integrated circuit device (DRAM) according to the embodiment 1 of the present invention;

[0021]FIG. 6 is a partial plan view of the substrate showing the manufacturing method of the semiconductor integrated circuit device (DRAM) according to the embodiment 1 of the present invention;

[0022]FIG. 7 is a partial cross sectional view of the substrate showing the manufacturing method of the semiconductor integrated circuit device (DRAM) according to the embodiment 1 of the present invention;

[0023]FIG. 8 is a partial cross sectional view of the substrate showing the manufacturing method of the semiconductor integrated circuit device (DRAM) according to the embodiment 1 of the present invention;

[0024]FIG. 9 is a partial cross sectional view of the substrate showing the manufacturing method of the semiconductor integrated circuit device (DRAM) according to the embodiment 1 of the present invention;

[0025]FIG. 10 is a partial cross sectional view of the substrate showing the manufacturing method of the semiconductor integrated circuit device (DRAM) according to the embodiment 1 of the present invention;

[0026]FIG. 11 is a partial plan view of the substrate showing the manufacturing method of the semiconductor integrated circuit device (DRAM) according to the embodiment 1 of the present invention;

[0027]FIG. 12 is a diagram for describing the effect of the embodiment of the present invention;

[0028]FIG. 13 is a diagram for describing the effect of the embodiment of the present invention;

[0029]FIG. 14 is a diagram for describing the effect of the embodiment of the present invention;

[0030]FIG. 15 is a diagram for describing the effect of the embodiment of the present invention;

[0031]FIG. 16 is a diagram for describing the effect of the embodiment of the present invention;

[0032]FIG. 17 is a partial cross sectional view of the substrate of the semiconductor integrated circuit device for describing the effect of the present embodiment of the present invention;

[0033]FIG. 18 is a partial cross sectional view of the substrate of the semiconductor integrated circuit device according to the embodiment 2 of the present invention;

[0034]FIG. 19 is a partial cross sectional view of the substrate of the semiconductor integrated circuit device according to the embodiment 3 of the present invention;

[0035]FIG. 20 is a partial cross sectional view of the substrate of the semiconductor integrated circuit device according to the embodiment 4 of the present invention;

[0036]FIG. 21 is a partial cross sectional view of the substrate for showing the manufacturing method of the semiconductor integrated circuit device according to the embodiment 1 of the present invention;

[0037]FIG. 22 is a partial cross sectional view of the substrate for showing the manufacturing method of the semiconductor integrated circuit device according to the embodiment 5 of the present invention;

[0038]FIG. 23 is a partial cross sectional view of the substrate for showing the manufacturing method of the semiconductor integrated circuit device according to the embodiment 5 of the present invention;

[0039]FIG. 24 is a partial cross sectional view of the substrate for showing the manufacturing method of the semiconductor integrated circuit device according to the embodiment 5 of the present invention;

[0040]FIG. 25 is a partial cross sectional view of the substrate for showing the manufacturing method of the semiconductor integrated circuit device according to the embodiment 5 of the present invention; and

[0041]FIG. 26 is a partial cross sectional view of the substrate for showing the manufacturing method of the semiconductor integrated circuit device according to the embodiment 5 of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0042] Embodiments of the present invention will be described in detail hereinafter with reference to the drawings. In all the drawings used for description of the embodiments, components having the same function are given the same characters respectively and the repeated description will be omitted.

[0043] (Embodiment 1)

[0044] An method for manufacturing a DRAM of an embodiment of the present invention will be described with reference to FIG. 1 to FIG. 11 in the order of step application.

[0045] At first, as shown in FIG. 1 and FIG. 2, a memory cell selection MISFET Qs is formed on the main surface of a semiconductor substrate 1 (p-type well 3 and active region L). One exemplary process for forming a memory cell selection MISFET Qs is shown hereinafter. FIG. 1 is a partial cross sectional view of a semiconductor substrate for showing the manufacturing process of a DRAM of the present embodiment, and FIG. 2 is a partial plan view of the semiconductor substrate for showing the manufacturing process of the DRAM of the present embodiment. FIG. 1 corresponds, for example, to the cross section along the line A-A in FIG. 2.

[0046] As shown in FIG. 2, an active region (L) is defined by an element separation 2, and the element separation 2 is formed as described hereinafter.

[0047] At first, the surface of the semiconductor substrate 1 is etched to form a groove, and a thin silicone oxide film (not shown in the drawing) is formed on the inside of the groove. Subsequently, a silicone oxide film 5 is deposited on the semiconductor substrate 1 including the inside of the groove by means of Chemical Vapor Deposition (CVD) technique, and the silicone oxide film 5 is polished by means of Chemical Mechanical Polishing (CMP) technique. Next, a p-type well 3 is formed by ion-implantation of B (Boron) into the semiconductor substrate 1. As the result, a narrow long active region (L) surrounded by the element separation 2 is formed as shown in FIG. 2. Two memory cell selection MISFETs Qs that use any one of a source and drain commonly are formed on each active region (L).

[0048] Subsequently, a memory cell selection MISFET Qa is formed. To form a memory cell selection MISFET Qs, at first the surface of the p-type well 3 is cleaned with HF (hydrofluoric acid)-base cleaning solution, a gate insulating film 8 is formed on the surface of the p-type well 3 (active region L) by means of thermal oxidation of the semiconductor substrate 1.

[0049] Next, a gate electrode (conductive member) G is formed on the top of the gate insulating film 8. To form the gate electrode G, at first an n-type polycrystalline silicon film 9 a doped with P (phosphorous), WN (tungsten nitride, not shown in the drawing) film, W (tungsten) film 9 b, and a silicone nitride film 10 are deposited successively in the order on the top of the gate insulating film 8. Thereafter, a silicone nitride film 10 is dry-etched with aid of a photoresist film (not shown in the drawing) as a mask. At that time, the silicone nitride film 10 remains on the region where a gate electrode is to be formed.

[0050] Next, the W film 9 b, WN film (not shown in the drawing), and polycrystalline silicon film 9 a are subjected to dry etching with aid of the silicone nitride film 10 as a mask to form a gate electrode G comprising the polycrystalline silicon film 9 a, WN film, and W film 9 b. Herein, the gate electrode G functions as a word line WL.

[0051] Next, so-called Wet Hydrogen oxidation is carried out in an atmosphere of H₂O and H₂ to form a thin oxide film (light oxide film) 11 a on the side wall of the polycrystalline silicon film 9 a. This oxide film is formed in order to improve the dielectric strength between the gate electrode and the source and drain regions. In this case, the silicon (polycrystalline silicon, silicon substrate) is selectively oxidized by means of Wet Hydrogen oxidation without oxidation of W film 9 b. Therefore, the abnormal oxidation of the W film 9 b can be prevented.

[0052] Next, n-type impurity (phosphorous) is injected to p-type wells 3 located on both sides of the gate electrode G to form an n-type semiconductor region 13.

[0053] Next, a silicone nitride film is deposited on the semiconductor substrate 1 by means of CVD technique, and the deposit is etched anisotropically to form a side wall film 16 on the side wall of the gate electrode G.

[0054] Next, as shown in FIG. 3 and FIG. 4, a silicone oxide film 19 is formed on the top of the semiconductor substrate 1 by means of CVD technique, and the top of the silicone oxide film 19 is polished by means of CMP technique to flatten the surface. FIG. 3 is a partial cross sectional view of the semiconductor substrate showing a manufacturing process of a DRAM of the present embodiment, and FIG. 4 is a partial plan view of the semiconductor substrate showing the manufacturing process of a DRAM of the present embodiment. FIG. 3 is corresponding to, for example, the cross section along the line A-A of FIG. 4.

[0055] Next, contact holes 20 and 21 are formed on the top of the n⁻-type semiconductor region 13, the surface of the semiconductor substrate 1 (n⁻-type semiconductor region 13) is exposed, n-type impurity (phosphorous) is ion-implanted into the p-type well 3 (n⁻-type semiconductor region 13) of the memory cell array section through the contact holes 20 and 21 to thereby form a n⁺-type semiconductor region 17.

[0056] Through the process described hereinabove, the memory cell selection MISFET Qs that constitutes the DRAM memory cell is completed.

[0057] Subsequently, a bit-line BL and capacitor (information storing capacitance element) C to be connected electrically to the n⁺-type semiconductor region 17 of the memory cell selection MISFET Qs are formed. Because the DRAM of the present embodiment has the above-mentioned COM structure, the capacitor C is formed after the bit-line BL has been formed. The process for forming the bit-line BL and the capacitor C will be described in detail hereinafter.

[0058] The bit-line BL and capacitor C are connected through the n⁺-type semiconductor region 17 of the memory cell selection MISFET Qs and a plug 22 (refer to FIG. 8 and FIG. 9).

[0059] The plug 22 is formed inside the contact holes 20 and 21 as shown in FIG. 5 and FIG. 6. FIG. 5 is a partial cross sectional view of the semiconductor substrate showing the manufacturing process of the DRAM of the present embodiment, and FIG. 6 is a partial plan view of the semiconductor substrate showing the manufacturing process of the DRAM of the present embodiment. FIG. 5 is correspond to, for example, the cross section along the line A-A of FIG. 6.

[0060] To form the plug 22, at first a low resistance polycrystalline silicon film doped with n-type impurity such as phosphorous (P) is deposited on the top of the silicone oxide film 19 including the inside of the contact holes 20 and 21 by means of CVD technique, and the polycrystalline silicon film is polished so as to remain only inside the contact holes 20 and 21 to form the plug 22.

[0061] Next, a silicone oxide film 23 is deposited on the top of the silicone oxide film 19 by means of CVD technique, a through hole 24 is formed by means of dry etching technique with aid of a photoresist film (not shown in the drawing) as a mask on the top of the plug 22 that has been formed inside the contact hole 21.

[0062] Next, a W film is deposited on the top of the silicone oxide film 23 including the inside of the through hole 24 by means of CVD technique, the W film formed on the top of the silicone oxide film 23 is polished by means of CMP technique so as to remain only inside the through hole 24 to thereby form a plug 26.

[0063] Next, a bit-line BL is formed on the top of the plug 26. The bit-line is formed, for example, by applying a method in which a W film is deposited on the top of the silicone oxide film 23 including the top of the plug 26 and the W film is subjected to dry etching with aid of a photoresist film (not shown in the drawing) as a mask. Though the bit-line BL cannot be seen on the cross section along the A-A line, a part of the plug 26 and the bit-line BL that are positioned upper than the cross section along the line A-A of FIG. 6 is shown in FIG. 5 (same as in FIG. 10) to show clearly the relation between the MISFET Qs (plug 22) and the bit-line BL.

[0064] Next, as shown in FIG. 7, a silicone oxide film 34 is deposited on the top of the silicone oxide film (insulating film) 23 including the top of the bit-line BL. FIG. 7 is, for example, corresponding to the cross section along the line B-B of FIG. 6 (same as in FIG. 8). As shown in the drawing, the bit-lines are disposed with a constant interval.

[0065] The silicone oxide film 34 on the bit line BL is formed by means of high density plasma CVD (referred to as HDP-CVD hereinafter) technique. Such silicone oxide film is referred to as HDP silicone oxide film hereinafter. The HDP-CVD involves CVD that is carried out in a low pressure and high electron density atmosphere. Regular plasma CVD is carried out in an atmosphere that the pressure is in a range from 1 to 10 Torr and the electron density is in a range from 1×10⁹ to 1×10¹⁰. On the other hand, HDP-CVD is carried out in an atmosphere that the pressure is in a range from 0.001 to 0.01 Torr and the electron density is 1×10¹² or higher. The film component is deposited (silicone oxide in this case) , and at that time etching is carried out by means of high density plasma simultaneously. Therefore, silicone oxide is penetrated into the deep inside of a groove even though the groove is a narrow and small groove (narrow space). Herein, the film forming temperature in this case (first temperature) is 700° C. or lower, and for example, the film forming temperature is 350 to 650° C. for the silicone oxide film 34.

[0066] Next, the semiconductor substrate 1 is subjected to RTA (Rapid Thermal Anneal, Lamp Anneal, heat treatment) for within 60 seconds at 750° C. (second temperature). The RTA involves heat treatment in which a light emitted from a lamp such as a tungsten-halogen lamp is irradiated onto the semiconductor substrate 1 (wafer) to heat it with radiation heat.

[0067] Next, the top of the HDP silicone oxide film 34 is polished by means of CMP technique to flatten the surface. Heat treatment may be applied after polishing. The HDP silicone oxide film 34 is to be served as an interlayer insulating film for insulation between the bit-line BL and a capacitor C, which will be described hereinafter.

[0068] As described hereinabove, according to the present embodiment, because heat treatment (RTA) is carried out after the HDP silicone oxide film 34 has been formed, the film stress caused by the HDP silicone oxide film 34 is reduced previously. As the result, the film stress exerted on the bit-line BL can be reduced even when high temperature treatment, for example, crystallization annealing of the capacitance insulating film (tantalum oxide film) of the capacitor C is carried out in the following process. Breakage and separation (pealing) of the bit-line BL can be reduced resultantly. Though RTA is carried out at 750° C. in the present embodiment, a RTA temperature that is higher than the film forming temperature of the HDP silicone oxide film 34 is more effective. By employing the RTA temperature that is equal to or higher than the crystallization annealing temperature, the stress that is the same level as exerted on the bit-line BL and HDP silicone oxide film 34 is relaxed in annealing.

[0069] The film stress of the silicone oxide film and W film of the bit-line BL will be described hereinafter. FIG. 12 is a diagram showing the film stress (MPa) change that occur when RTA (heat treatment) is carried out for 60 seconds at 750° C. The abscissa in the drawing shows the type of film. W donates Wm, P-SiN donates a silicone nitride film formed by means of plasma CVD technique, HDP donates a HDP silicone oxide film, and TEOS donates a silicone oxide film formed by means of CVD technique from ozone (O₃) and tetraethoxy-silane used as the raw material (referred to as TEOS film hereinafter). The stress is exerted on the semiconductor substrate (wafer) so as to deform concave in the positive stress region, and so as to deform convex in the negative stress region.

[0070] As shown in the drawing, in the case of the W film, the film stress changes from approximately 900 MPa to approximately 500 MPa between before and after RTA, and that means the stress change of approximately −400 MPa. Furthermore, in the case of the HDP silicone oxide film, the film stress changes from approximately −180 MPa to approximately −80 MPa, and that means the film stress change of approximately +100 MPa. In the case of the TEOS film, the film stress changes from approximately −120 MPa to approximately −105 MPa, and that means the film stress change of approximately +15 MPa.

[0071] On the other hand, in the case of a silicone nitride film formed by means of plasma CVD technique, the film stress changes from approximately −200 MPa to approximately 150 MPa, and that means the film stress change of approximately +350 MPa. As described hereinabove, in the case of the insulating film such as silicone oxide film and silicone nitride film, the film stress changes in the positive direction due to RTA. In other words, these film changes so that the wafer is deformed concave, and on the other hand the metal film such as W film changes so that the wafer is deformed convex due to RTA.

[0072] Therefore, if these films that are laminated is subjected to RTA, adhesion surface of the film is separated due to stress change of various films and the thin pattern such as wiring is broken. Particularly, in the case that the bit-line BL width is 0.12 μm or thinner to form highly integrated DRAM, breakage and separation occur easily. Furthermore, as described hereinabove, because the stress change direction is different between an insulating film and metal film, breakage and separation occur easily the more.

[0073] For example, a silicone nitride film 40 is formed as the etching stopper when a groove in which the capacitor C is to be formed is formed, which will be described hereinafter in detail. Furthermore, a silicone oxide film 41 is deposited on the top of the silicone nitride film 40, and the capacitance insulating film (tantalum oxide film) of the capacitor C is subjected to crystallization annealing thereafter. If the stress of these films (bit-line BL, HDP silicone oxide film 34, silicone nitride film 40, and silicone oxide film 41) change differently each other when the capacitor C is annealed, a strong stress is exerted on the bit-line BL in a short time to cause breakage or separation of the bit-line BL.

[0074] However, according to the present embodiment, because the bit-line BL on which the HDP silicone oxide film 34 has been deposited is subjected to RTA, the film stress due to the HDP silicone oxide film 34 is reduced previously.

[0075] Next, the temperature rising speed of RTA will be described. FIG. 12 shows two temperature rising conditions of RTA, and FIG. 14 shows plots of the yield obtained when the treatment is carried out under the temperature rising conditions shown in FIG. 13 for various bit-line BL widths (μm).

[0076] The solid line (a) shown in FIG. 13 shows the temperature rising condition in which the temperature is risen at a speed of approximately 20° C./second from a temperature near 500° C. that is the film forming temperature of the HDP silicone oxide film 34. On the other hand, the broken line (b) shows the temperature rising condition in which the temperature is risen at a speed of 60° C./second continuously from the beginning to the temperature higher than 500° C. for the treatment.

[0077] These temperature rising conditions are applied to DRAMs having various bit-line BL widths and the yield is measured. As the result, it is found that in the case of the temperature rising condition (b) (square marks), the yield of 90% or more is obtained for the bit-line width of approximately 0.12 μm, but the yield decreases as the bit-line width decreases, and the yield of 75% is obtained for the bit-line width of 0.11 μm. On the other hand, it is found that in the case of the temperature rising condition (a) (rhomboid marks) , the yield of 90% or more is obtained over the whole bit-line width range from 0.13 μm to 0.1 μm, and in some cases the yield of nearly 100% is obtained.

[0078] As described hereinbefore, the slow temperature rising, for example, RTA temperature rising speed of 60° C./second or slower allows the stress exerted on the bit-line to be relaxed, and breakage and separation of the bit-line can be prevented. As the result, the yield can be improved. It is not necessary to slow down the temperature rising speed up to the film forming temperature of the silicone oxide film, and the temperature rising speed may be slowed down after the film forming temperature of the silicone oxide film. Furthermore, RTA temperature rising speed can be controlled by controlling the lamp output.

[0079] Furthermore, in the present embodiment, because the structure in which a single layer (only the HDP silicone oxide film 34) is interposed between the bit-line BL and the capacitor C, which will be described hereinafter, and the top surface is flattened by means of CMP technique, occurrence of foreign matter is suppressed.

[0080] In detail, as shown in the embodiment 4, though it is possible to flatten the surface by use of an SOG (Spin On Glass) film, in this case, it is necessary to employ a structure in which the SOG film is interposed between dense TEOS films on the top and bottom in order to reinforcing the strength of the interlayer insulating film and in order to avoid the effect of moisture generated from the SOG film. In this case, it is necessary to form the TEOS film, SOG film, and TEOS film successively on the bit-line BL, such process can result in remainder foreign matter between these films. Particularly, as described hereinafter, because the SOG film is a coated film and formed in an equipment different from the equipment for forming the TEOS film, the foreign matter likely comes on the film surface when the film is transferred between equipments.

[0081] The amount of foreign matter after the interlayer insulating film is formed for insulation between the bit-line BL and the capacitor C is shown in FIG. 15 and FIG. 16. FIG. 15 shows the foreign matter amount in the case of the interlayer insulating film having three-layer structure comprising the TEOS film, SOG film, and TEOS film, and on the other hand FIG. 16 shows the foreign matter amount in the case of the interlayer insulating film having single-layer structure comprising the silicone oxide film only. As shown in FIG. 15 and FIG. 16, the number of wafers containing the foreign matter amount of “22 to 33” is largest in the case of the three-layer interlayer insulating film, and the number of wafers containing the foreign matter amount of “44 to 55” is next largest and the numbers for “33 to 44” and “55 to 66” decrease in this order. Furthermore, the number of wafers containing the foreign matter amount range from 22 to 66 occupies approximately 74% of the whole. On the other hand, the number of wafers containing the foreign matter amount of “0 to 10” is largest in the case of the single-layer interlayer insulating film, and the total number of wafers containing the foreign matter amount range from 0 to 20 occupies approximately 96% of the whole. As described hereinabove, occurrence of foreign matter can be suppressed.

[0082] The effect described hereinafter is obtained by use of no SOG. As described hereinafter, a plug 39 served for electrical connection between the memory cell selection MISFET Qs and the capacitor C is formed in the interlayer insulating film for insulation between the bit-line and the capacitor C. The plug is formed by embedding a conductive film consisting of W in a contact hole formed in the interlayer insulating film.

[0083] However, if the interlayer insulating film has the SOG film, moisture and gas generated from the SOG film remain in the contact hole when the conductive film is embedded, and the conductive film can be embedded insufficiently. As the result, voids B are formed in the plug as shown in FIG. 17 to cause connection failure.

[0084] However, in the present embodiment, the structure in which the signal layer (only HDP silicone oxide film 34) is used between the bit-line BL and the capacitor C, which will be described hereinafter, and the top is flattened by means of CMP technique is employed, the above-mentioned connection failure is suppressed.

[0085] Subsequently, a process for forming the capacitor C and the plug 39 that is served to electrically connect between the capacitor C and the memory cell selection MISFET Qs will be described.

[0086] At first, as shown in FIG. 9 to FIG. 11, the HDP silicone oxide film 34 and the silicone oxide film 23 that is laminated under the HDP silicone oxide film 34 are subjected to dry etching to from a through hole 38 on the top of the plug 22 formed in the contact hole 20. Next, a W film is deposited on the top of the HDP silicone oxide film 34 including the inside of the through hole 38 by means of CVD technique, the W film formed on the top of the HDP silicone oxide film 34 is polished by means of CMP technique so as to remain only inside the through hole to thereby form the plug 39. FIG. 9 is a cross sectional view along the line A-A of FIG. 11, and FIG. 10 is a cross sectional view along the line B-B of FIG. 11. Herein, according to the present embodiment, because a SOG film that is apt to generate moisture and gas is not used in the interlayer insulating film as described hereinabove, the W film is deposited accurately inside the through hole 38. As the result, the contact failure between the plug 39 and the plug 22 located under the plug 39 is suppressed.

[0087] Next, the capacitor C is formed. To form the capacitor C, at first a silicone nitride film 40 is formed on the top of the HDP silicone oxide film 34 by means of plasma CVD technique, and a silicone oxide film 41 is formed on the top of the silicone nitride film 40 subsequently by means of CVD technique. Then, the silicone oxide film 41 and the silicone nitride film 40 are subjected to dry etching to form a groove 42 on the top of the through hole 38. The silicone nitride film 40 is served as a stopper when the silicone oxide film 41 is etched. Furthermore, a thick silicone oxide film 41 is formed to increase the surface area of the groove 42, and the increased surface area of the capacitance insulating film formed inside can be formed. As the result, the capacitance of the capacitor can be increased.

[0088] Next, a low resistance polycrystalline silicon film doped with n-type impurity such as phosphorus (P) is deposited on the top of the silicone oxide film 41 including the inside of the groove 42 by means of CVD technique, and a photoresist film is embedded in the groove 42. Then, the polycrystalline silicone film formed on the top of the silicone oxide film 41 is etched back so as to remain only on the inside wall of the groove 42. Thereby, the bottom electrode 43 of the capacitor C is formed along the inside wall of the groove 42.

[0089] Next, a tantalum oxide film 44 that is to be served as the capacitance insulating film (dielectric film) is deposited inside the groove 42 on which the bottom electrode 43 has been formed and on the silicone oxide film 41. The tantalum oxide film 44 is deposited by use of penta-ethoxy tantalum (Ta(OC₂H₅)₅) and oxygen as the raw material.

[0090] Next, to improve the film quality of the tantalum oxide film 44, the tantalum oxide film 44 is subjected to heat treatment (anneal) at a temperature of 700° C. or higher. The tantalum oxide film 4,4 is crystallized by heat, treatment. Furthermore, the defect in the tantalum oxide film 44 is restored by heat treatment, and the leak current is reduced.

[0091] As described hereinabove, according to the present embodiment, because RTA (heat treatment) is applied after the HDP silicone oxide film 34 has been formed and the film stress caused by the bit-line BL and the HDP silicone oxide film 34 is reduced previously, the film stress exerted on the bit-line BL is reduced when the tantalum oxide film 44 is annealed to crystallize it, and breakage and separation of the bit-line BL are suppressed. Herein, in the present embodiment, tantalum oxide is used as the capacitance insulating film, but for example, high/strong dielectric material such as lead titanate zirconate may be used. Because crystallization annealing is required also for such film, the same effect is obtained by heat treatment of the HDP silicone oxide film 34.

[0092] Next, a TiN film 45 that is to be served as the top electrode 45 is deposited on the tantalum oxide film 44 by means of CVD technique so that the inside of the groove 42 is filled.

[0093] Thereby, the capacitor C comprising the bottom electrode 33 formed of a polycrystalline silicon film, the capacitance insulation film 44 formed of the tantalum oxide film, and the top electrode 45 formed of the TiN film is formed. Furthermore, the memory cell of the DRAM comprising the memory cell selection MISFET Qs and the capacitor C connected in series to the memory cell selection MISFET Qs is completed through the process described hereinabove. FIG. 11 is a partial plan view of the semiconductor substrate on which the capacitor C has been formed.

[0094] Thereafter, a silicone oxide film 50 and a wiring 55 consisting of Al (aluminum) are formed on the top of the capacitor C. Further, a silicone oxide film and wiring are formed and a surface protection film is formed on the top of the silicone oxide film and wiring, though these components are omitted in the drawing.

[0095] (Embodiment 2)

[0096] The HDP-CVD film (HDP silicone oxide film 34) is used as the interlayer insulating film for insulation between the bit-line BL and the capacitor C in the embodiment 1, however, a TEOS film formed by means of plasma CVD technique may be used as the interlayer insulating film. Excepting the process for forming the interlayer insulating film for insulation between the bit-line BL and the capacitor C, the process for forming the bit line BL (FIG. 1 to FIG. 6), the process for forming the plug 39, and the following process are the same as those applied in the embodiment 1, and therefore the description will be omitted.

[0097] At first, a semiconductor substrate on which a bit-line BL has been formed is provided, and a TEOS film 234 is deposited on the top of the bit line BL and a silicone oxide film 23 formed under the bit-line BL as shown in FIG. 18. FIG. 18 is a partial cross sectional view of the semiconductor substrate for showing the manufacturing process of a DRAM of the present embodiment. For example, FIG. 18 is corresponding to the B-B cross section of FIG. 11. In FIG. 18, layers located under the silicone oxide film 23 (for example, plug 22 and element separation 2) are omitted (also in FIG. 19 and FIG. 20 described hereinafter).

[0098] The TEOS film 234 is formed by means of plasma CVD technique by use of tetraethoxy-silane and ozone (O₃) as the raw material as described hereinbefore. At that time, the film forming temperature (first temperature) is equal to or lower than 450° C., and for example, in the case of the TEOS film 234, a film forming temperature of 400° C. is employed.

[0099] Next, the semiconductor substrate 1 is subjected to RTA (Rapid Thermal Anneal, heat treatment) at 750° C. for 60 seconds or shorter. RTA involves irradiation of a lamp light emitted from a tungsten-halogen lamp onto the semiconductor substrate 1 (wafer), and the semiconductor substrate 1 is heated with radiation heat.

[0100] Next, the surface of the TEOS film 234 is polished by means of CMP technique to flatten the surface. It is desirable to polish the TEOS film 234 covering the region located under the void B because the void B is generated in the TEOS film 234 while it is being formed as shown in FIG. 18. If the void remains, slurry used in CMP remains to cause foreign matter and to form uneven surface of the TEOS film 234. As the result, the focus precision becomes poor when a contact hole formed in the TEOS film 234 and the pattern to be located on the TEOS film 234 are subjected to photolithography.

[0101] The above-mentioned heat treatment may be carried out after polishing. The TEOS film 234 is to be served as the interlayer insulating film for insulation between the bit-line BL and a capacitor C, which will be described hereinafter.

[0102] As described hereinabove, according to the present embodiment, because the heat treatment is carried out after the TEOS film 234 has been formed as in the case of the embodiment 1, the film stress caused by the TEOS film 234 is reduced previously. Therefore, even though high temperature heat treatment, for example, crystallization annealing of the capacitance insulating film (tantalum oxide film) of the capacitor C is carried out in the following process, the film stress exerted on the bit-line BL is reduced, and breakage and separation of the bit-line BL are suppressed. Though RTA is carried out at 750° C. in the present embodiment, the effect is obtained by employing an RTA temperature equal to or higher than the film forming temperature of the TEOS film 234. Furthermore, by employing the RTA temperature equal to or higher than the crystallization annealing temperature, the stress that is the same as the stress exerted on the bit-line BL and TEOS film 234 in annealing is relaxed.

[0103] Furthermore, because a single layer (only TEOS film 234) is interposed between the bit-line BL and the capacitor C and the surface is flattened by means of CMP technique in the present embodiment, generation of foreign matter is suppressed as in the case of the embodiment 1. Yet furthermore, because a single layer (only TEOS film 234) is interposed between the bit-line BL and the capacitor C, which will be described hereinafter, and an SOG film that is apt to generate moisture and gas is not used, a W film is deposited inside the through hole 38 precisely, and the contact failure between the plug 39 and the plug 22 located under the plug 39 is suppressed as the result.

[0104] Subsequently, the capacitor C and the plug 39 for electrical connection between the capacitor C and the memory cell selection MISFET Qs are formed. However, the description of the forming process is omitted because the forming process is the same as that carried out in the embodiment 1 described with reference to FIG. 9 to FIG. 11.

[0105] (Embodiment 3)

[0106] The HDP-CVD film (HDP silicone oxide film 34) is used as the interlayer insulating film for insulation between the bit-line BL and the capacitor C in the embodiment 1, but instead a laminate film comprising an HDP silicone oxide film and a TEOS film may be used as the interlayer insulating film. Excepting the process for forming the interlayer insulating film for insulation between the bit-line BL and the capacitor C, the process for forming the bit line BL (FIG. 1 to FIG. 6), the process for forming the plug 39, and the following process are the same as those applied in the embodiment 1, and therefore the description will be omitted.

[0107] At first, a semiconductor substrate on which a bit-line BL has been formed is provided, and an HDP silicone oxide film 334 a is deposited on the top of the bit line BL and a silicone oxide film 23 formed under the bit-line BL by means of HDP-CVD technique as shown in FIG. 19 as in the case of the embodiment 1. Silicone oxide can be embedded into the deep inside of the groove even though the groove is small and narrow (narrow space) by means of HDP-CVD technique. Herein, the film forming temperature applied for film forming is equal to or lower than 450° C. (first temperature). Next, a TEOS film 334 b is formed on the HDP silicone oxide film 334 a by means of CVD technique by use of ozone (O₃) and tetraethoxy-silane as the raw material. At that time, the film forming temperature is equal to or lower than 450° C., and for example, the film forming temperature is 400° C. in the case of this TEOS film 334 b.

[0108] Next, the semiconductor substrate 1 is subjected to RTA at 750° C. (second temperature) for 60 seconds or shorter. RTA involves irradiation of a lamp light emitted from a tungsten-halogen lamp onto the semiconductor substrate 1 (wafer), and the semiconductor substrate 1 is heated with radiation heat.

[0109] Next, the top of the TEOS film 334 b is polished by means of CMP technique to flatten the surface. Instead, RTA may be carried out after polishing. A laminate film comprising the silicone oxide film 334 a and the TEOS film 334 b is to be served as the interlayer insulating film for insulation between the bit-line BL and the capacitor C, which will be described hereinafter.

[0110] As described hereinabove, according to the present embodiment, because the silicone oxide film 334 a is formed by means of HDP-CVD technique and the TEOS film 334 b is formed on the silicone oxide film 334 a, the thickness of the silicone oxide film is secured, and the polishing precision can be improved.

[0111] Furthermore, as in the case of the embodiment 1, because RTA (heat treatment) is carried out after the silicone oxide film 334 a and the TEOS film 334 b have been formed, the film stress caused from these films is reduced previously. Therefore, even though-high temperature heat treatment, for example, crystallization annealing of the capacitance insulating film (tantalum oxide film) of the capacitor C is carried out in the following process, the film stress exerted on the bit-line BL is reduced, and breakage and separation of the bit-line BL are suppressed. Though RTA is carried out at 750° C. in the present embodiment, the effect is obtained by employing an RTA temperature equal to or higher than the film forming temperature of the HDP silicone oxide film 334 a and TEOS film 334 b. Furthermore, by employing the RTA temperature equal to or higher than the crystallization annealing temperature, the stress that is the same as the stress exerted on the bit-line BL, the HDP silicone oxide film 334 a, and the TEOS film 334 b in annealing is relaxed.

[0112] Furthermore, because an SOG film that is apt to generate moisture and gas is not used between the bit-line BL and the capacitor C, which will be described hereinafter, a W film is deposited inside the through hole 38 precisely, and the contact failure between the plug 39 and the plug 22 located under the plug 39 is suppressed as the result.

[0113] Subsequently, the capacitor C and the plug 39 for electrical connection between the capacitor C and the memory cell selection MISFET Qs are formed. However, the description of the forming process is omitted because the forming process is the same as that carried out in the embodiment 1 described with reference to FIG. 9 to FIG. 11.

[0114] (Embodiment 4)

[0115] The laminate film comprising the HDP-CVD film and TEOS film is used as the interlayer insulating film for insulation between the bit-line BL and the capacitor C in the embodiment 1, however, a three-layer structure comprising a TEOS film, an SOG film (coating film) , and a TEOS film may be used as the interlayer insulating film. Excepting the process for forming the interlayer insulating film for insulation between the bit-line BL and the capacitor C, the process for forming the bit line BL (FIG. 1 to FIG. 6) , the process for forming the plug 39, and the following process (FIG. 9 to FIG. 11) are the same as those applied in the embodiment 1, and therefore the description will be omitted.

[0116] At first, a semiconductor substrate on which a bit-line BL has been formed is provided, and a TEOS film 434 a is deposited on the top of the bit line BL and a silicone oxide film 23 formed under the bit-line BL as shown in FIG. 20 by means of CVD technique by use of ozone (O₃) and tetraethoxy-silane as the raw material. At that time, the film forming temperature (first temperature) is equal to or lower than 450° C., and for example, in the case of the TEOS film 434 a, a film forming temperature of 400° C. is employed. Next, the SOG film 434 b is coated on the TEOS film 434 a.

[0117] Next, the semiconductor substrate 1 is subjected to RTA (Rapid Thermal Anneal, heat treatment) at 750° C. (second temperature) for 60 seconds or shorter. RTA involves irradiation of a lamp light emitted from a tungsten-halogen lamp onto the semiconductor substrate 1 (wafer), and the semiconductor substrate 1 is heated with radiation heat.

[0118] Next, the TEOS film 434 c is deposited in the same manner as used for depositing the TEOS film 434 a on the SOG film 434 b. Instead, RTA may be carried out after the TEOS film 434 c has been formed. The laminate film comprising the TEOS film, SOG film, and TEOS film is to be served as the interlayer insulating film for insulation between the bit-line BL and the capacitor C, which will be described hereinafter.

[0119] As described hereinabove, according to the present embodiment, because a laminate film comprising the TEOS film, SOG film, and TEOS film, which are used generally, is used as the interlayer insulating film, an interlayer insulating film can be formed easily at a low cost.

[0120] Furthermore, because heat treatment is carried out at a temperature equal to or higher than 750° C., namely a crystallization annealing temperature of the capacitance insulating film (tantalum oxide film) of the capacitor C, after the laminate film has been formed, the film stress caused from these films is reduced previously, and the film stress exerted on the bit-line BL in crystallization annealing is reduced. As the result, breakage and separation of the bit-line BL are suppressed. RTA is carried out at 750° C. in the present embodiment, but the annealing temperature is by no means limited to 750° C., and by employing the RTA temperature equal to or higher than the crystallization annealing temperature, the stress that is the same as the stress exerted on the bit-line BL, the SOG film, and TEOS film in annealing is relaxed.

[0121] Subsequently, the capacitor C and the plug 39 for electrical connection between the capacitor C and the memory cell selection MISFET Qs are formed. However, the description of the forming process is omitted because the forming process is the same as that carried out in the embodiment 1 described with reference to FIG. 9 to FIG. 11.

[0122] (Embodiment 5)

[0123] A method for manufacturing a semiconductor integrated circuit device will be described hereinafter with reference to FIG. 21 to FIG. 26 in the order of successive steps.

[0124] At first, a semiconductor element is formed on the main surface of a semiconductor substrate 1. FIG. 21 shows an exemplary case in which an n-channel type MISFET Qn and a p-channel type MISFET Qp are formed as the semiconductor element. These MISFET Qn and Qp are formed according to the usual MISFET forming process.

[0125] An exemplary usual MISFET forming process is described hereinafter.

[0126] At first, an element separation 2 is formed on the semiconductor substrate 1 consisting of p-type single crystalline silicon in the same manner as used in the embodiment 1.

[0127] Next, p-type impurity and n-type impurity are ion-implanted into the substrate 1, and the substrate 1 is heat treated to diffuse the impurity to thereby form p-type well 3 and n-type well 4.

[0128] Thereafter, a gate oxide film 8 is formed on the surface of the respective p-type well 3 and n-type well 4 by means of thermal oxidation. Next, a low resistance polycrystalline silicon film 9 doped with phosphorus is deposited on the top of the gate oxide film 8 by means of CVD technique, and subsequently a silicone nitride film 10 is deposited on the top of the low resistance polycrystalline silicon film 9 by means of CVD technique.

[0129] Next, the silicone nitride film 10 is subjected to dry etching so that the silicone nitride film 10 remains on the region where a gate electrode is to be formed. Then, the polycrystalline silicon film 9 is subjected to dry etching with aid of the silicone nitride film 10 as the mask to form a gate electrode 9.

[0130] Next, n-type impurity is ion-implanted into the p-type well 3 located on both sides of the gate electrode 9 to thereby form a n-type semiconductor region 13, and p-type impurity is ion-implanted into the n-type well 4 to thereby form a p-type semiconductor region 14.

[0131] Next, a silicone nitride film is deposited on the substrate 1 by means of CVD technique, and the silicone nitride film is etched anisotropically to thereby form a side wall film 16 on the side wall of the gate electrode 9.

[0132] Next, n-type impurity is ion-implanted into the p-type well 3 to thereby form an n⁺-type semiconductor region 17 (source, drain), and p-type impurity is ion-implanted into the n-type well 4 to thereby form a p⁺-type semiconductor region 18 (source, drain).

[0133] By applying the process described hereinabove, the n-channel type MISFET Qn and p-channel type MISFET Qp having LDD (Lightly Doped Drain)-structured source and drain are formed.

[0134] Next, a silicone oxide film 51 is deposited on the MISFET Qn and Qp by means of CVD technique, and then the top of the silicone oxide film 51 is polished to flatten the surface.

[0135] Next, a photoresist film (not shown in the drawing) is formed on the silicone oxide film 51, and the silicone oxide film 51 is etched with aid of the photoresist film as the mask to thereby form a contact hole C1 on the n⁺-type semiconductor region 17 and the p⁺-type semiconductor region 18 located on the main surface of the semiconductor substrate 1.

[0136] Next, a thin TiN film is formed on the silicone oxide film 51 including the inside of the contact hole C1 by means of CVD technique and then a W film is deposited by means of CVD technique. Then, the TiN film and W film deposited outside the contact hole C1 are polished by means of CMP technique so that these films remain only inside the contact hole C1 to thereby form a plug P1.

[0137] Next, as shown in FIG. 22, a TiN film and W film are deposited successively on the silicone oxide film 51 and the plug P1 and patterned in the desired configuration to thereby form a first layer wiring M1.

[0138] Next, as shown in FIG. 23, a silicone oxide film 52 is deposited on the first layer wiring M1 and silicone oxide film 51. The silicone oxide film 52 is formed by means of high density plasma CVD technique. By employing high density plasma CVD technique, silicone oxide is filled into the deep inside of the groove even though the groove width is narrow and small (small space) as described in the embodiment 1. At that time, the film forming temperature is equal to 700° C. or lower, for example, a temperature in a range from 350° C. to 650° C. is applied in the case of the silicone oxide film 52.

[0139] Next, the semiconductor substrate 1 is subjected to RTA (Rapid Thermal Anneal, lamp anneal, heat treatment) at 750° C. (second temperature) for 60 seconds or shorter. RTA involves irradiation of a lamp light emitted from a tungsten-halogen lamp onto the semiconductor substrate 1 (wafer), and the semiconductor substrate 1 is heated with radiation heat.

[0140] Next, as shown in FIG. 24, the top of the silicone oxide film 52 is polished by means of CMP technique to flatten the surface.

[0141] As described hereinabove, according to the present embodiment, because heat treatment is carried out after the silicone oxide film 52 has been formed, the film stress caused by the silicone oxide film 52 is reduced previously. Therefore, even though high temperature heat treatment, for example, high temperature treatment applied when the TiN (titanium nitride) film that constitutes the plug P2 is deposited by means of CVD technique, the film stress exerted on the wiring M1 is reduced, and breakage and separation of the bit-line BL are suppressed.

[0142] Thereafter, as shown in FIG. 25, a photoresist film (not shown in the drawing) is formed on the silicone oxide film (insulating film) 52, and the silicone oxide film 52 is etched with aid of the photoresist film as the mask to thereby form a contact hole C2 on the first layer wiring M1.

[0143] Next, a thin TiN film (conductive layer) is formed on the silicone oxide film 52 including inside the contact hole C2 by means of CVD technique, and then a W film (conductive layer) is deposited by means of CVD technique. Thereafter, the TiN film and W film deposited outside the contact hole C2 are polished by means of CMP technique so that these films remain only inside the contact hole C2 to thereby form a plug P2. This TiN (titanium nitride) film functions as a barrier metal film and is deposited at a temperature in a range from approximately 600 to 650° C. In this embodiment the TiN film is formed at 630° C.

[0144] As described hereinabove, according to the present embodiment, because heat treatment is carried out after the silicone oxide film 52 has been formed and the film stress caused by the wiring M1 and the silicone oxide film 52 is reduced previously, the film stress exerted on the wiring M1 is reduced, and breakage and separation of the wiring M1 are suppressed. RTA is carried out at 750° C. in the present embodiment, but by employing the RTA temperature equal to or higher than the film forming temperature of the silicone oxide film 52, the effect is obtained initially. Furthermore, by employing the RTA temperature equal to or higher than the film forming temperature of the TiN film, the stress that is the same as the stress exerted on the bit-line BL and silicone oxide film 52 in the process is relaxed.

[0145] Next, as shown in FIG. 26, a TiN film and W film are deposited successively on the silicone oxide film 52 and plug P2 and patterned in a desired configuration to thereby form the second layer wiring (conductive layer) M2. The second layer wiring M2 comprises the TiN film and W film in the present embodiment, but otherwise Al (Aluminum) or Cu (Copper) may be used instead. Next, a silicone oxide film 53 is deposited on the second layer wiring M2 and silicone oxide film 52.

[0146] By repeating the forming process of a plug, wiring, and interlayer insulating film (silicone oxide film), the wiring of three layers or more is formed, and the description of the following process is omitted.

[0147] Furthermore, RTA (heat treatment) is applied to the silicone oxide film 52 in the present embodiment, but otherwise heat treatment may be applied to the silicone oxide films 51 and 53 or the insulating film located above the third layer wiring (not shown in the drawing).

[0148] The invention accomplished by the inventors of the present invention is described hereinbefore in detail based on the embodiments, however, the present invention, is by no means limited to the above-mentioned embodiments, various modifications may be applied without departing from the spirit and the scope of the invention.

[0149] Particularly, in the above-mentioned embodiments, the present invention is applied to the insulating film formed on a bit-line of a DRAM or the insulating film on wiring, however, the present invention may be applied widely to the insulating film on a conductive layer that is subjected to heat treatment after forming.

[0150] Effects obtained by applying inventions that are representative among the inventions disclosed in the present patent application are described hereinafter.

[0151] (1) A second insulating film is formed at the first temperature so as to cover the wiring and then the second insulating film is subjected to heat treatment at the second temperature that is higher than the above-mentioned first temperature, and furthermore a first electrode, dielectric film, and second electrode are formed on the above-mentioned second insulating film. As the result, the film stress exerted on the wiring is reduced and breakage and separation of the wiring are prevented when the dielectric film is subjected to heat treatment process.

[0152] (2) Because the second insulating film is formed so as to cover the wiring and the above-mentioned second insulating film is subjected to heat treatment at the first temperature, when the above-mentioned second insulating film is etched to form an aperture on the above-mentioned second insulating film and the first conductive layer is formed inside the above-mentioned aperture at the second temperature by means of chemical vapor deposition technique, the film stress exerted on the wiring is reduced and breakage and separation of the wiring are prevented.

[0153] As the result of the above, the performance of a semiconductor integrated circuit device having the above-mentioned wiring is improved. 

What is claimed is:
 1. A method for manufacturing a semiconductor integrated circuit device comprising the steps of: (a) forming a first insulating film over a semiconductor substrate; (b) forming a plurality of wirings on the first insulating film; (c) forming a second insulating film at the first temperature so as to cover the wirings; (d) heat-treating the second insulating film at the second temperature; (e) forming a first electrode, dielectric film, and second electrode on the second insulating film; wherein the second temperature is higher than the first temperature.
 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the second insulating film is formed by means of chemical vapor deposition technique in which high density plasma is used.
 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the step for forming the dielectric film includes a step for heat-treating the dielectric film at the third temperature that is equal to or lower than the second temperature.
 4. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first insulating film is polished between the step (a) and the step (b).
 5. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the second insulating film is polished between the step (c) and the step (d).
 6. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein the heat treatment of the second insulating film is carried out before the second insulating film is polished.
 7. The method for manufacturing a semiconductor integrated circuit device according to claim 1, further comprising the steps of, before the step (a): (f) forming a plurality of conductive pieces on the semiconductor substrate with interposition of the third insulating film; and (g) forming a pair of semiconductor regions on the semiconductor substrate surface on both ends of the conductive piece, wherein the wiring is connected to the one of the paired semiconductor regions and the first electrode is connected to the other of the paired semiconductor regions.
 8. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the wiring is formed of tungsten.
 9. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein lamp anneal technique is employed for the heat treatment.
 10. The method for manufacturing a semiconductor integrated circuit device according to claim 9, wherein in the heat treatment the temperature reaches the second temperature through the first stage in which the temperature rising speed is fast and the second stage in which the temperature rising speed is slower than the temperature rising speed in the first stage.
 11. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the dielectric film is a tantalum oxide film.
 12. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the dielectric film is a lead titanate zirconate film.
 13. A method for manufacturing a semiconductor integrated circuit device comprising the steps of: (a) forming a first insulating film over a semiconductor substrate; (b) forming a plurality of wirings on the first insulating film; (c) forming a second insulating film so as to cover the wirings by means of chemical vapor deposition technique; (d) forming a third insulating film, that is a coated film, on the second insulating film, and for heat-treating it at the first temperature; (e) forming a fourth insulating film on the third insulating film by means of chemical vapor deposition technique; and (f) forming a first electrode, dielectric film, and second electrode on the fourth insulating film, wherein the step for forming the dielectric film includes a step for heat treating the dielectric film at the second temperature, and wherein the first temperature is equal to or higher than the second temperature.
 14. A method for manufacturing a semiconductor integrated circuit device comprising the steps of: (a) forming a first insulating film over a semiconductor substrate; (b) forming a plurality of wirings on the first insulating film; (c) forming a second insulating film so as to cover the wirings; (d) heat-treating the second insulating film at the first temperature; (e) etching the second insulating film so that the surface of the wiring is exposed to form an aperture on the second insulating film; (f) forming a first conductive layer inside the aperture at the second temperature by means of chemical vapor deposition technique; (g) forming a second conductive layer on the first conductive layer; and (h) polishing the first and second conductive layers so that the first and second conductive layers remain selectively inside the aperture, wherein the first temperature is equal to or higher than the second temperature.
 15. The method for manufacturing a semiconductor integrated circuit device according to claim 14, wherein the wiring is a tungsten film.
 16. The method for manufacturing a semiconductor integrated circuit device according to claim 15, wherein the first conductive layer is a titanium nitride layer.
 17. The method for manufacturing a semiconductor integrated circuit device according to claim 14, wherein the second insulating film is formed by means of chemical vapor deposition technique in which high density plasma is used.
 18. The method for manufacturing a semiconductor integrated circuit device according to claim 14, further comprising a step for forming a third conductive layer on the second insulating film and the second conductive layer.
 19. The method for manufacturing a semiconductor integrated circuit device according to claim 18, wherein the third conductive layer comprises an aluminum layer.
 20. The method for manufacturing a semiconductor integrated circuit device according to claim 18, wherein the third conductive layer comprises a copper layer. 